Take a Phenom II quad core CPU – get rid of the behemoth 6 MB L3 cache, double the L2 cache to 4 MB, tweak its power consumption, all in 32 nm and you get the Llano CPU – in highly simplified terms.
The Block diagram above explains the Llano APU under the hood. Each of the 4 Cores get their own L2 Cache. There is no L3 Cache. This interconnect arrangement highly simplifies the architecture and the potential development time as compared to Intel’s Ring Bus architecture in the Sandy Bridge with L3 Cache. The higher L3 Cache does not necessarily improve the things at its large size leads to longer latency. The L3 Cache would also lead to higher power consumption. The L1 Cache comprises of 64 KB of data and 64 KB of instruction Cache ( total 128 KB) per core – the same as in the Athlon II and Phenom II.
The Core itself are basically the same design as the Athlon II and Phenom II with some tweaks that will give 6% or so performance for the same clock. There is added power and clock advantage that inherits by moving to 32 nm from 45 nm in Athlon II and Phenom II.
Other improvements include hardware prefetcher, and larger buffer sizes. We will not go into the details. Just bear in mind the “broad” 6% advantage the cores in Llano have over the Athlon II and Phenom II.