While Clock to Clock CPU performance do not see any significant or improvement in IVB as compared to the SNB, the power consumption study is very interesting in the Ivy Bridge.
Take a close look at the graph below that plots the CPU core voltage on the X axis versus the Transistor Gate delay on the Y-Axis. The Transistor Gate delay is loosely related to the maximum frequency that the processor can operate.
The Top curve belongs to the 32 nm Planar technology. The Planar word is used to differentiate it from the latest 3D technology ( also called Tri Gate process) used in the current Ivy Bridge 22 nm manufacturing Process. The middle curve is for the 22 nm Planar manufacturing process while the bottom most one is for the 22 nm Tri – Gate process.
For the moment focus on the horizontal brown line. At 1.0 V operating voltage the normalized Gate delay is 1.0 for the 32 nm planar process. Keeping the Gate Delay same, the 22 nm Tri-Gate process would require only about 0.77 volts – dramatically reducing the power requirement. You can operate the Ivy Bridge at about 75% of the core voltage keeping the performance same. This is where we can get lower TDP parts while keeping the performance same.
But the left part of the curve is more interesting. It tells us something that recent trend of the Ultra Thin notebooks will benefit from. At low voltage ( around 0.7V) , the transistor gate delay in 3D 22 nm process reduces by 37% as compared to the Planar 32 nm ( notice that this difference is mere 18% at regular voltage). An ultra low voltage Ivy Bridge part will be 37% faster than than the corresponding Ultra Voltage Sandy Bridge Part. At 1.0V this gain is 18%. The Lower voltage parts stand to gain more than the regular parts.