As stated earlier, Ivy Bridge is mainly a 22 nm die shrink of the Sandy Bridge and there is no fundamental change in the processor architecture. We have more or less the same Sandy Bridge architecture, the same L3 Cache. But there are few tweaks here and there which will bring close to 5% performance improvement.
There has been a change in the way resource allocation to Hyper Threading queue takes place. The Ivy Bridge now dynamically allocates resources to threads. This is helpful if there is only a single thread active, all the resources will be dedicated to that thread. If this is effective, the difference in the performance with and without Hyperthreading will be more visible ( let us see this when the Pentium Ivy Bridge and Core i3 Ivy Bridge launches).
The Floating Point and Integer divider has twice the throughput of the Sandy Bridge. While the Integer divider will show small improvement, the FP divider, which is computationally more complex should show substantial improvement.
There is some change in the MOV instruction execution. In the IVB MOV is executed by pointing one register at the location of the destination register.
The are couple of Industry Standard Architecture changes – most important of these are inclusion of very high speed DRNF (digital random number generator) and supervisory mode execution protection (SMEP).
As you can see – there is no significant change in the Ivy Bridge processor architecture. It is basically a 22 nm die shrink – at least from the processor core perspective.